I’m very excited for RISC-V adoption in the desktop to become mainstream, as it could help to break the duopoly of x86 CPUs by Intel and AMD and encourage more competition, resulting in better value CPUs for us consumers! Being an open standard, any company can improve upon RISC-V, add additional features, make it more efficient, etc. But aside from this point, I haven’t really heard much information about other advantages of RISC-V.
Could RISC-V theoretically be more efficient than ARM, more performant, etc.? Of course, currently, it isn’t, since most software isn’t optimised for RISC-V CPUs and companies have only just started developing them, but if it’s adopted at a scale like x86 in desktop computers or ARM in mobile devices and servers, would it perform better than the x86 or ARM equivalent? Being a newer architecture (2014) than both x86 (1978 for 16-bit) and ARM (1985), does it have additional QoL improvements over the older architectures?
The main problem with RISC-V is that it is far from mature. Which leads to both slow hardware and lack of software.
And while anyone can contribute to the open design, more advanced improvisations will remain proprietary.
Another problem is that the RISC-V landscape is far from uniform. Vendor A has this command set, vendor B a different one. Yes, the core set is the same, but the interesting, more advanced features have split. And not just like Intel and AMD had once split about the X86 command set, but with many smaller vendors. Intel and AMD managed to get things back together. Will RISC-V accomplish the same?
For enterprises, it’s like SaaS vs lifetime license. ARM has restrictions on target market, volume, integration, etc. If you go the RISCV route, you pay once for the design but then the HW is yours to do as you please.
For academia RISCV allows open discussions all the way down for a complete system. Before RISCV can around a lot of academia was splintered around different old chips instead of cutting edge tech.
Current open source RISCV cores aren’t that far behind. They are roughly 2-3x slower for peak performance and maybe a little behind the Pareto frontier as compared to ARM/x86. Commercial cores are even closer within 20-50% depending on which benchmark you believe. A move from open source to commercial or vice versa is possible without impacting the rest of your stack. This is not what happens if you use ARM
I can’t say I’ve looked too much at RISC-V (yet), but someone once painted the following picture for me: if AMD and Intel are duking it out for supercomputers, while ARM works its way up to servers and down to microcontrollers, who serves the absolute smallest use-cases? As in, what if my whizz-bang product genuinely only needs a 300 Hz – not MHz, not kHz – processor to do some truly banal calculations? How can I possibly convince a silicon fab to build such a niche and tiny chip at scale?
In this context, scale would be however many could fit a single 300 mm wafer, and takes into account the fixed cost of the wafer itself, and then the price premium for smaller manufacturing process that would fit more chips onto the same wafer. At such low clock frequencies, the chip could be made using ancient lithography machines for dirt cheap.
But ARM would almost certainly not entertain the request to do consulting work for such an incredibly low-end chip, where the ARMv8 and v9 architectures would be vastly overpowered.
For these sorts of economically infeasible ideas, RISC-V brings to the table the possibility that some small-batch ASIC consulting firm would work with their customers to churn out some mindboggling processor designs. Because when the architecture is free (as in beer and as in speech), it releases the designers from constraints that today’s designs must have.
For that use case you use a microcontroller, and go to sleep. You can get a full rpi2040 32 bit uC for under a dollar, an attiny for about 30 cents. Sometimes you can solve the problem with a 555 for about 5 cents.
At those prices it’s absolutely not worth it to develop a custom new chip, no matter the architecture.
You don’t need an advanced cpu with tight design tolerances for that.
While true, RISC-V probably isn’t the architecture for that. Better to use an old architecture whose patents have expired, and implement it on a new, smaller process.
RISC-V is good as an alternative to ARMv8 where the use case doesn’t quite fit what ARM is doing — or to implement in a country where there may be restrictions on how ARM is sold/deployed.
What I’m waiting for is for someone to implement something in RISC-V similar to Apple’s ARM implementation, with all the cores and memory on a single die. No need to do FPGA when you can just fab an unencumbered design in small batches for relatively cheap.
Better to use an old architecture whose patents have expired, and implement it on a new, smaller process.
I’m not aware of any examples of an old architecture that was largely reused while ported to a new process, without requiring extensive redesigning of the analog components. Old processor architectures are a product of their day, making assumptions and decisions about the silicon paths that would be wholly invalidated if brought as-is to more-modern processes. It is nowhere near as simple as a copy/paste job of SystemVerilog or RTL.
To invest even one hour of design time to update, say, the 1970s Intel 4004 design (10 micrometer process) into the 2000s (130 nm) would be more expensive than just using RISC-V for free, which has already been fabricated using 22 nm, among other processes.
The MC68000, for example, is over 40 years old and out of patent. It’s been repackaged on a smaller process as the 68SEC000, and there are Verilog implementations available too.
And that’s just the example that’s top of mind. There’s a whole line of low frequency Atmel processors too, but those are still very much in patent and so mostly tangential to this conversation.
RISC-V doesn’t really make sense for simpler implementations though; you’d still have to do a bunch of work to simplify it, AND end up with an architecture very few are currently familiar with.
Once Chinese implementations of RISC-V become endemic and there are enough people familiar with the architecture, it might make sense to start creating custom subsets on simplified processes. But we’re still years away from that.
RISC-V is already being used in a decent number of electronics as an additional single purpose processor
The most important part is probably that it is a green field design, meaning they aren’t limited by backwards compatibility.
As for the specifics of risc-v? The option to chose a subset of the instructions (organized as extensions) allows for a more gradual tradeoff between price and performance in embedded devices.
On the desktop and server end, the vector instructions seem like the next logical step after simd, but my expertise there is limited.
